1. Field of the Invention
The present invention relates to a semiconductor memory circuit apparatus, and, more particularly, to a semiconductor memory circuit apparatus having a complementary MOS random access memory (RAM).
2. Description of the Related Art
FIG. 1 illustrates a conventional memory (RAM) circuit portion of this type, and FIG. 2 a timing chart of individual signals in a case where this memory circuit is incorporated in a microcomputer-installed semiconductor memory circuit apparatus, a reference clock for operating the microcomputer, etc., is used, and the read operation for the RAM circuit portion is controlled by the microcomputer.
FIG. 4 illustrates that the individual signals for operating the RAM are prepared from a chip enable signal CE by means of an inverter circuit delay and capacitors, shown in FIG. 3, in order to quicken the read operation.
Referring to FIGS. 1 and 2, a description will be given below of the read operation at the time the RAM circuit portion is activated using a reference clock .phi.. To begin with, "A.sub.O to A.sub.n " in FIG. 1 denote address signals, and RAM cells 101 are arranged in a m.times.n matrix. A circuit 109 is a sense amplifier circuit for fixing the potential level quickly to a low ("L") level when data starts moving from a selected one of the RAM cells to one of a pair of bus lines BUS and BUS, e.g., to the one having an "L" level. This circuit 109, which is operational by a sense signal SENSE, reads data by clocked inverter 111, and outputs data Data (A). A circuit 110 serves to write data in the RAM cells 101, and receives a control signal Write and write data Data (B). A transistor T.sub.6 serves to precharge the bus lines BUS and BUS, and is controlled by a control signal Pre. An enable signal Enable serves to prevent word lines WL.sub.l to WL.sub.n in a non-selected state from being selected while the addresses A.sub.O to A.sub.n are being changed; the signal Enable is often prepared from a chip enable signal (CE).
Assuming that, in FIG. 2, the address ADDRESS is changed and settled at the rising of the reference clock .phi. and the precharge signal Pre changes to a "H" (high) level from "L", the bus lines BUS and BUS in FIG. 1 maintain the "H" level.
When the enable signal Enable changes to "H" from "L", one of N NAND circuits 102 is selected to output a select signal of level "H" from an inverter 103 to one of the word lines WL.sub.l to WL.sub.n. This "H"-level signal is transferred to the end of the word line through a polysilicon wire constituting that word line. When the potential level of the word line WL (one of WL.sub.l to WL.sub.n) exceeds the threshold voltage of a transistor T.sub.2, as shown in FIG. 9, the charge accumulated in a load capacitor C.sub.1 connected to the bus line BUS is discharged through the transistor T.sub.2 having its gate electrode as a word line, from that one of the nodes of two inverters in the RAM cell which is outputting an "L"-level signal, 120 in the diagram. As a result, as shown in FIG. 1, the bus line BUS side keeps the "H" level while the level of the bus line BUS side starts moving toward "L." When the potentials of both bus lines become different from each other, the sense amplifier 109 performs the sensing operation, and the BUS side is supplied with an "H" level signal by the amplifier 109 while the BUS side sharply changes its level to "L," becoming stable at the ground level. The signal on the bus line BUS can, therefore, be taken as data Data (A) in response to a read signal .phi. read.
As described above referring to FIG. 2, the use of the reference clock .phi. can sequentially enable the individual signals, which operate the RAM circuit portion, and is significantly effective. Since the operation depends on the clock, however, this system is very unstable in high-speed operation.
FIG. 3 illustrates a circuit in which in order to improve the operational speed of the RAM circuit portion in FIG. 1, the individual signals necessary for the read operation of the RAM circuit are prepared by delaying a chip enable signal (CE) or a chip select signal (CS), which enables the memory operation, through an inverter 241, a NOR circuit 242 and a capacitor C.
Since the individual RAM control signals are determined by the time needed for charging/discharging the capacitor C, this circuit ensures a quicker operation than the one shown in FIG. 2.
It can therefore be said that the circuit in FIG. 2 which uses the reference clock .phi. is suitable for low-speed and middle-speed operations, whereas the one shown in FIG. 3 is suitable for a high-speed operation. According to the circuit in FIG. 3, however, when the source voltage of the semiconductor circuit apparatus changes, the ON resistance of transistors constituting the inverter 241 changes, varying the time needed for charging/discharging the capacitor C. The times from the falling of the chip enable signal (CE) to the points at which the individual signals Pre, Enable, SENSE and .phi. read are prepared, would considerably vary depending on the source voltage in use. In some cases, therefore, when the word line WL.sub.l is selected, for example, the sense amplifier 109 performs the sense operation before the "H" level signal for rendering the transistor T.sub.2 on reaches the end of that word line, and if there is no potential difference between BUS and BUS, the BUS side, which should be set at the "L" level, becomes "H" and the BUS side, which should have the " H" level, becomes "L" due to the influence of the operational noise or a like cause. In addition, even if a signal of the level to turn on the transistor T.sub.2 reaches the end of the word line thereafter, the output buffer performance of the sense amplifier is normally greater, and the levels of the BUS and BUS are not easily changed. It may sometimes happen that data in the RAM cells 101 will vary due to the action of transistor T.sub.2.
As the number of the RAM cells in the horizontal direction (m) increases, as in the equivalent circuit in FIG. 10B of the portion shown in FIG. 10A, the resistance R' of the polysilicon wire constituting a word line, and the transfer gate capacitance C.sub.G, floating capacitance, etc. of each RAM cell become too large. As a result, the time constant .tau.=CR of the word line WL becomes a dominant factor for the signal delay time at the vicinity of the end of that word line. Therefore, reducing the ON resistance of the transistors of a word-line driving output inverter 105 (corresponding to 103 in FIG. 1) does not quicken the signal delay time. The apparatus in FIG. 3 having a voltage-dependent circuit and large-capacity RAM cells would cause a time difference between the signal delay of the word line and the timing of the control signals shown in FIG. 4, or restrict the source voltage in use.
FIG. 5 illustrates a conventional circuit in which an NOR circuit 130 and an inverter 131 are provided in light of the signal delay of the word line, and the sense amplifier 109 is operated accordingly. This circuit has many wires up to the NOR circuit 130 in order to detect a selected one of the n word lines, requiring a comparative size of an area for the wiring region and the NOR circuit 130, etc., in the semiconductor circuit apparatus.
If the signal delay on the word line is determined by the time constant CR or the like, when the read operation or write operation is completed, the time indicated by T.sub.12 in FIG. 4 becomes too short to set the end of the word line to "L" from "H" in a case where the circuit, like the one shown in FIG. 3, is voltage-dependent . As a result, the precharge transistor T.sub.6 is turned on while the transfer gate T.sub.2 in the RAM cell 101 in FIG. 1 is not completely turned off, generating a current path from the V.sub.DD voltage supply to BUS, transistor T.sub.2, transistor T.sub.1 and to ground. This phenomenon should not necessarily occur in one RAM cell; a comparative number of paths would occur at the vicinity of the end of the word line, thus increasing the through current between voltage supplies as well as current consumption.
As described above, the conventional semiconductor memory circuit apparatuses have the following shortcomings:
(1) With the use of a reference clock .phi. (FIG. 2) used in a microcomputer, the RAM operation is controlled by the clock, limiting high-speed operation. This system is therefore not suitable for high-speed operation. In addition, some systems may not use a clock as the base for various control signals.
(2) If control signals are prepared by delaying the chip enable signal CE, chip select signal, etc., using the inverter delay and drain capacitance or the like in order to ensure high-speed operation of the RAM circuit portion, a change in source voltage varies the ON resistance of the transistors constituting an inverter, altering the signal delay. As a result, the sense timing changes, etc., which causes the normal operation range of the RAM circuit portion to appear as source-voltage dependency. This may restrict the range of the source voltage in use.
(3) As the memory capacity of RAM increases and the word line becomes longer, the delay of signals traveling on the word line is determined by the time constant .tau.=CR which is determined by the resistance R of the word line and the gate capacitance C hanging therefrom. Therefore, the resultant, delayed signals are unlikely to have a certain relativity to the voltage-dependent control signals prepared in the above case (2).
(4) A variation caused by the fabrication of semiconductor memory apparatuses, i.e., a variation in time constant .tau. (such as a variation in resistance R of the polysilicon wire constituting the word line, a variation in gate capacity C hanging from the word line, etc.) is not proportional to the fabrication-oriented variation in the circuit shown in FIG. 3 (such as a variation in the junction capacity), the normal operation range may be restricted as in the case of (3). This causes a yield reduction as said to occur in producing semiconductor memory circuit apparatuses.
(5) The employment of the NOR logic of each word line as shown in FIG. 5, inevitably increases the wiring area and the area of the logic circuit necessary for preparing the NOR circuit 130.
(6) At the time the NOR circuit is placed in an unselected status after completion of the read/write operation, when the time constant of the word line is large and the precharge signal of the circuit in FIG. 5 becomes an enable status quickly, the transfer gate T.sub.2 at the vicinity of the end of the word line for reading data from the RAM cell would not be completely turned off, generating the through current.